Synthesizing Hardware from Dataflow Programs

Jörn W. Janneck (1) , Ian D. Miller (2) , David B. Parlour (3) , Ghislain Roquier (4) , Matthieu Wipliez (5) , Mickaël Raulet (5)

1 Xilinx Inc.
2 siXis Inc
3 Tabula Inc.
4 EPFL - Ecole Polytechnique Fédérale de Lausanne
5 IETR - Institut d'Electronique et de Télécommunications de Rennes

The MPEG Reconfigurable Video Coding working group is developing a new library-based process for building the reference codecs of future MPEG standards, which is based on dataflow and uses an actor language called Cal. The paper presents a code generator producing RTL targeting FPGAs for Cal, outlines its structure, and demonstrates its performance on an MPEG-4 Simple Profile decoder. The resulting implementation is smaller and faster than a comparable RTL reference design, and the second half of the paper discusses some of the reasons for this counter-intuitive result.

Domaines: Systèmes embarqués

Jörn W. Janneck, Ian D. Miller, David B. Parlour, Ghislain Roquier, Matthieu Wipliez, et al.. Synthesizing Hardware from Dataflow Programs. Journal of Signal Processing Systems, 2011, 63 (2), pp.241-249. ⟨10.1007/s11265-009-0397-5⟩. ⟨hal-00407947⟩