Hardware code generation from dataflow programs

Nicolas Siret (1, 2) , Matthieu Wipliez (1) , Jean Francois Nezan (3) , Aimad Rhatay (2)

1 IETR - Institut d'Electronique et de Télécommunications de Rennes
2 LTD - LeadTech Design
3 IETR - Institut d'Électronique et des Technologies du numéRique

The elaboration of new systems on embedded targets is becoming more and more complex. In particular, multimedia devices are now implemented using mixed hardware and software architecture, which improve the computational power but also increase the design complexity and the time to market. New design flows have been developed to help designers in the development of complex architecture. These design flows are often based on the use of languages with a higher level of abstraction. RVC-CAL is a dataflow programming language which provides the good features in this context. An RVC-CAL dataflow program can be compiled to various target software languages (e.g. C, Java, LLVM) with the Open RVC-CAL Compiler (Orcc). In this paper, we will present a new hardware code generator that generates a high-quality portable VHDL code with hierarchical architecture from a RVC-CAL dataflow program in a matter of seconds. The paper explains the underlying principles of the hardware code generator, and presents the results obtained from an Inverse DCT described as an RVC-CAL dataflow program.

Domaines: Systèmes embarqués

Nicolas Siret, Matthieu Wipliez, Jean Francois Nezan, Aimad Rhatay. Hardware code generation from dataflow programs. Design and Architectures for Signal and Image Processing (DASIP), 2010 Conference on, 2010, United Kingdom. pp.113 -120, ⟨10.1109/DASIP.2010.5706254⟩. ⟨hal-00565300⟩