Design of a Processor Optimized for Syntax Parsing in Video Decoders

Nicolas Siret (1) , Jean François Nezan (1) , Aimad Rhatay (2)

1 IETR - Institut d'Electronique et de Télécommunications de Rennes
2 LTD - LeadTech Design

Heterogeneous platforms aim to offer both performance and flexibility by providing designers processors and programmable logical units on a single platform. Processors implemented on these platforms are usually soft-cores (e.g. Altera NIOS) or ASIC (e.g. ARM Cortex-A8). However, these processors still face limitations in terms of performance compared to full hardware designs in particular for real-time video decoding applications. We present in this paper an innovative approach to improve performance using both a processor optimized for the syntax parsing (an Application-Specific Instruction-set Processor) and a FPGA. The case study has been synthesized on a Xilinx FPGA at a frequency of 100MHz and we estimate the performance that could be obtained with an ASIC.

Mots clés: Application-Specific Instruction-set Processor (ASIP); embedded processor; processor architecture; Instruction Set Architecture (ISA); bit manipulation operations; video decoding; circuit design; multimedia

Domaines: Electronique; Traitement du signal et de l'image [eess.SP]; Traitement du signal et de l'image [eess.SP]

Nicolas Siret, Jean François Nezan, Aimad Rhatay. Design of a Processor Optimized for Syntax Parsing in Video Decoders. Conference on Design and Architectures for Signal and Image Processing (DASIP), Nov 2011, Tampere, Finland. pp.CD. ⟨hal-00661330⟩