Low Overhead Fault-Tolerance Technique for Dynamically Reconfigurable Softcore Processor
Résumé
In this paper, we propose a new approach to implement a reliable softcore processor on SRAM-based FPGAs, which can
mitigate radiation-induced temporary faults (single-event upsets (SEUs)) at moderate cost. A new Enhanced Lockstep scheme built
using a pair of MicroBlaze cores is proposed and implemented on Xilinx Virtex-5 FPGA. Unlike the basic lockstep scheme, ours allows
to detect and eliminate its internal temporary configuration upsets without interrupting normal functioning. Faults are detected and
eliminated using a Configuration Engine built on the basis of the PicoBlaze core which, to avoid a single point of failure, is implemented
as fault-tolerant using triple modular redundancy (TMR). A softcore processor can recover from configuration upsets through partial
reconfiguration combined with roll-forward recovery. SEUs affecting logic which are significantly less likely than those affecting
configuration are handled by checkpointing and rollback. Finally, to handle permanent faults, the tiling technique is also proposed. The
new Enhanced Lockstep scheme requires significantly shorter error recovery time compared to conventional lockstep scheme and
uses significantly smaller number of slices compared to known TMR-based design (although at the cost of longer error recovery time).
The efficiency of the proposed approach was validated through fault injection experiments.