Generation of Efficient High-Level Hardware Code from Dataflow Programs

Nicolas Siret (1, 2) , Matthieu Wipliez (1, 2) , Jean François Nezan (1, 2) , Francesca Palumbo (3)

1 IETR - Institut d'Électronique et des Technologies du numéRique
2 UEB - Université européenne de Bretagne - European University of Brittany
3 UniCa - Università degli Studi di Cagliari = University of Cagliari

High-level synthesis (HLS) aims at reducing the time-to-market by providing an automated design process that interprets and compiles high-level abstraction programs into hardware. However, HLS tools still face limitations regarding the performance of the generated code, due to the difficulties of compiling input imperative languages into efficient hardware code. Moreover the hardware code generated by the HLS tools is usually target-dependant and at a low level of abstraction (i.e. gate-level). A generated code at a high-level of abstraction (i.e. chip-level) is better suited to the needs of systems' architects because they can understand and control all of the design processes. We propose in this paper a new approach to HLS to generate efficient, high-level hardware code from Dataflow Programs. Implementation results (from two dynamic dataflow programs) on Xilinx, Altera and Latice FPGAs and on ASIC targeting 90nm CMOS technology are also presented.

Mots clés: dataflow models; high level synthesis

Domaines: Multimédia [cs.MM]; Génie logiciel [cs.SE]; Langage de programmation [cs.PL]; Electronique

Nicolas Siret, Matthieu Wipliez, Jean François Nezan, Francesca Palumbo. Generation of Efficient High-Level Hardware Code from Dataflow Programs. Design, Automation and test in Europe (DATE), Mar 2012, Dresden, Germany. pp.NC. ⟨hal-00763804⟩