New Digital Block Implementation Algorithm for MIMO Channel Hardware Simulator

Mouhammad Malli (1) , Bachir Habib (1) , Gheorghe Zaharia (1) , Ghaïs El Zein (1) , Youssef Nasser (2) , Karim Kabalan (2)

1 IETR - Institut d'Électronique et des Technologies du numéRique
2 Department of mathematics [Beirut]

The hardware simulator facilitates the test and validation cycles by replicating channel artifacts in a controllable and repeatable laboratory environment. After a description of the MIMO channel models and the hardware simulator architecture, this paper presents new implementation algorithm of its digital block. The proposed algorithm allows the selection of specific environments and various scenarios, standards (LTE or WLAN 802.11ac) and Doppler speeds to implement the digital block architecture. The digital block architecture is implemented for 2×2 MIMO channel on a Xilinx Virtex-IV FPGA using batch and command line files. The occupation on the FPGA, the accuracy of the output signals and the latencies of the architecture for each configuration are then analyzed.

Mots clés: Hardware simulator; FPGA; MIMO channels; LTE; WLAN 802.11 ac; implementation algorithm

Domaines: Electronique

Mouhammad Malli, Bachir Habib, Gheorghe Zaharia, Ghaïs El Zein, Youssef Nasser, et al.. New Digital Block Implementation Algorithm for MIMO Channel Hardware Simulator. 13th Mediterranean Microwave Symposium (MMS), Sep 2013, Saida, Lebanon. pp.1-4. ⟨hal-00871084⟩