P-type and N-type multi-gate polycrystalline silicon vertical thin film transistors based on low-temperature technology

Peng Zhang (1) , Emmanuel Jacques (1) , Regis Rogel (1) , Olivier Bonnaud (1)

1 IETR - Institut d'Électronique et des Technologies du numéRique

P-type and N-type multi-gate vertical thin film transistors (vertical TFTs) have been fabricated, adopting the low-temperature (T ⩽ 600 °C) polycrystalline silicon (polysilicon) technology. Stacked heavily-doped polysilicon source and drain are electrically isolated by an insulating barrier. Multi-teeth configuration is defined by reactive ion etching leading to sidewalls formation on which undoped polysilicon active layer is deposited. All the polysilicon layers are deposited from low pressure chemical vapor deposition (LPCVD) technique. Vertical TFTs are designed with multi gates, in order to have a higher equivalent channel width. Different active layer thicknesses have been attempted, and an ION/IOFF ratio slightly higher than 105 is obtained. P-type and N-type vertical TFTs have shown symmetric electrical characteristics. Different geometrical parameters have been chosen. IOFF is proportional to the single channel width, and to the tooth number. ION is only proportional to the tooth number. These devices open the way of a CMOS-like technology.

Mots clés: Polycrystalline silicon; 3D structure; Plasma etching; Thin film transistor (TFT)

Domaines: Electronique

Peng Zhang, Emmanuel Jacques, Regis Rogel, Olivier Bonnaud. P-type and N-type multi-gate polycrystalline silicon vertical thin film transistors based on low-temperature technology. Solid-State Electronics, 2013, 86, pp.1-5. ⟨10.1016/j.sse.2013.04.021⟩. ⟨hal-00906019⟩