System level synthesis of dataflow programs: HEVC decoder case study

Mariem Abid (1) , Khaled Jerbi (1) , Mickaël Raulet (1) , Olivier Déforges (1) , Mohamed Abid (2)

1 IETR - Institut d'Électronique et des Technologies du numéRique
2 CES

While dealing with increasing complexity of signal processing algorithms, the primary motivation for the development of High-Level Synthesis (HLS) tools for the automatic generation of Register Transfer Level (RTL) description from high-level description language is the reduction of time-to-market. However, most existing HLS tools operate at the component level, thus the entire system is not taken into consideration. We provide an original technique that raises the level of abstraction to the system level in order to obtain RTL description from a dataflow description. First, we design image processing algorithms using an actor oriented language under the Reconfigurable Video Coding (RVC) standard. Once the design is achieved, we use a dataflow compilation infrastructure called Open RVC-CAL Compiler (Orcc) to generate a C-based code. Afterward, a Xilinx HLS tool called Vivado is used for an automatic generation of synthesizable hardware implementation. In this paper, we show that a simulated hardware code generation of High Efficiency Video Coding (HEVC) under the RVC specifications is rapidly obtained with promising preliminary results.

Domaines: Traitement du signal et de l'image [eess.SP]; Traitement du signal et de l'image [eess.SP]

Mariem Abid, Khaled Jerbi, Mickaël Raulet, Olivier Déforges, Mohamed Abid. System level synthesis of dataflow programs: HEVC decoder case study. Electronic System Level Synthesis Conference (ESLsyn), 2013, May 2013, Austin, TX, United States. ⟨hal-00916809⟩