Built-in 3-Dimensional hamming multiple-error correcting scheme to mitigate radiation effects in SRAM-based FPGAs
Résumé
SRAM-based FPGAs have been employed extensively in many applications to implement adaptable systems whose functionalities can be changed at runtime. Unfortunately, even in terrestrial applications the SRAM con guration memory of FPGA devices is highly susceptible to radiation which may cause not only single but also multiple errors in physically adjacent memory cells, called Multiple Bit Upsets (MBUs). This paper proposes a new built-in 3-Dimensional Hamming (3DH) error correcting scheme to mitigate MBUs. The estimations of the probability of occurrence of undetected multiple errors indicate signi cant improvement of the error correction capabilities of the 3DH scheme proposed here, compared to known 2DH and IDH schemes. The other important advantage of the new scheme is that it can provide faster recon guration of con guration frames a ected by multiple errors, because error correction can be done using internal bus alone.