OCEAN, a flexible adaptive Network-on-Chip for dynamic applications

Ludovic Devaux (1) , Sébastien Pillement (2)

1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
2 IETR - Institut d'Électronique et des Technologies du numéRique

The dynamic and partial reconfiguration of FPGAs enables the dynamic placement of applicatives tasks in reconfigurable zones. However, the dynamic management of the tasks impacts the communications since they are not present in the FPGA during all computation time. So, the task manager should ensure the allocation of each new task and their interconnection which is performed by a flexible interconnection network. In this article, various interconnection networks are studied. Each architecture is evaluated with respect to its suitability for the paradigm of the dynamic and partial reconfiguration in FPGA implementations. This study leads us to propose the OCEAN network that supports the communication constraints into the context of dynamic reconfigurations. Thanks to a generic platform allowing in situ characterizations of network performances, fair comparisons of various Networks-On-Chip can be realized. The FPGA and ASICs implementations of the OCEAN network are also discussed.

Mots clés: Network on chip; dynamic and partial reconfiguration; FPGA; ASIC; OCEAN

Domaines: Sciences de l'ingénieur [physics]

Ludovic Devaux, Sébastien Pillement. OCEAN, a flexible adaptive Network-on-Chip for dynamic applications. Microprocessors and Microsystems: Embedded Hardware Design , 2014, 38 (4), pp. 337-357. ⟨10.1016/j.micpro.2014.02.002⟩. ⟨hal-00944214⟩