Stretching the edges of SVM traffic classification with FPGA acceleration

Tristan Groleat (1, 2) , Matthieu Arzel (3, 4) , Sandrine Vaton (1, 2)

1 REOP - Réseaux d'opérateurs
2 INFO - Département informatique
3 ELEC - Département Electronique
4 Lab-STICC_TB_CACS_IAS

Analyzing the composition of Internet traffic has many applications nowadays, like tracking bandwidth-consuming applications, QoS-based traffic engineering and lawful interception of illegal traffic. Even though many classification methods, such as Support Vector Machines (SVMs) have demonstrated their accuracy, few practical implementations of lightweight classifiers exist. As SVM has been proven to provide good accuracy, and is challenging to implement at high speeds, we consider in this paper the design of a real-time SVM traffic classifier at hundreds of Gb/s to allow online detection of categories of applications. We show the limits of software implementation and offer a solution based on the massive parallelism and lowlevel network interface access of FPGA boards. We also improve this solution by testing algorithmic changes that dramatically simplify hardware implementation. We then find theoretical maximum supported bit rates up to 473 Gb/s for the most challenging trace on a Virtex 5 FPGA, and confirm them through experimental performance results on a Combov2 board with a 10 Gb/s interface.

Mots clés: FPGA; Acceleration; Traffic classification; Network monitoring; SVM

Domaines: Réseaux et télécommunications [cs.NI]

Tristan Groleat, Matthieu Arzel, Sandrine Vaton. Stretching the edges of SVM traffic classification with FPGA acceleration. IEEE Transactions on Network and Service Management, 2014, 11 (3), pp.1-14. ⟨10.1109/TNSM.2014.2346075⟩. ⟨hal-01058332⟩