Parallel SHVC decoder: Implementation and analysis - Université de Rennes Accéder directement au contenu
Communication Dans Un Congrès Année : 2014

Parallel SHVC decoder: Implementation and analysis

Résumé

The new Scalable High efficiency Video Coding (SHVC) standard is based on a multi-loop coding structure which requires the total decoding of all intermediate layers. The decoding complexity becomes then a real issue, especially for a real time decoding of ultra high video resolutions. A parallel processing architecture is proposed to reduce both the decoding time and the latency of the SHVC decoder. The proposed solution combines the high level parallel processing solutions defined in the HEVC standard with an extension of the frame-based parallelism. The latter solution enables the decoding of several spatial and temporal SHVC frames in parallel to enhance both decoding frame rate and latency. The wavefront parallel processing solution is used for more coarse level of granularity. The proposed hybrid parallel processing approach achieves a near optimal speedup and provides a good trade-off between decoding time, latency and memory usage. On a 6 cores Xeon processor, the parallel SHVC decoder performs a real time decoding of 1600p60 video resolution.
Fichier principal
Vignette du fichier
PID3216551.pdf (372.54 Ko) Télécharger le fichier
Origine : Fichiers produits par l'(les) auteur(s)
Loading...

Dates et versions

hal-01068632 , version 1 (26-09-2014)

Identifiants

  • HAL Id : hal-01068632 , version 1

Citer

Wassim Hamidouche, Mickaël Raulet, Olivier Deforges. Parallel SHVC decoder: Implementation and analysis. Multimedia and Expo (ICME), 2014 IEEE International Conference on, Jul 2014, chengdu, China. pp.1-6. ⟨hal-01068632⟩
220 Consultations
734 Téléchargements

Partager

Gmail Facebook X LinkedIn More