Multi-core software architecture for the scalable HEVC decoder

Wassim Hamidouche (1) , Mickaël Raulet (1) , Olivier Deforges (1)

1 IETR - Institut d'Électronique et des Technologies du numéRique

The scalable high efficiency video coding (SHVC) standard aims to provide features of temporal, spatial and quality scalability. In this paper we investigate a pipeline and parallel software architecture for the SHVC decoder. The proposed architecture is based on the OpenHEVC software which implements the high efficiency video coding (HEVC) decoder. The architecture of the SHVC decoder enables two levels of parallelism. The first level decodes the base layer and the enhancement layers in parallel. The second level of parallelism performs the decoding of both the base layer and enhancement layers in parallel through the HEVC high level parallel processing solutions, including tile and wavefront. Up to the best of our knowledge, it is the first real time and parallel software implementation of the SHVC decoder. On an Intel Xeon processor running at 3.2 GHz, the SHVC decoder reaches the decoding of 1600p enhancement layer at 40 fps for x1.5 spatial scalability with using six concurent threads.

Mots clés: software architecture; HEVC decoder; Intel Xeon processor; OpenHEVC software; SHVC; enhancement layers; frequency 3.2 GHz; high efficiency video coding standard; multicore software architecture; Decoding; Encoding; Parallel processing; Pipelines; Scalability; Standards; Video coding; HEVC; High level parallel processing and wavefront parallel processing; Scalable HEVC; codecs; microprocessor chips

Domaines: Systèmes embarqués

Wassim Hamidouche, Mickaël Raulet, Olivier Deforges. Multi-core software architecture for the scalable HEVC decoder. Acoustics, Speech and Signal Processing (ICASSP), 2014 IEEE International Conference on, May 2014, Florence, Italy. pp.7545-7549. ⟨hal-01068829⟩