Fast approximately timed simulation

Vania Joloboff (1, 2) , Shenpeng Wang (3) , Yangdong Deng (3)

1 TEA - Tim, Events and Architectures
2 TEMPO - Trustworthy EMbedded PlatfOrms
3 THU - Tsinghua University [Beijing]

In this paper we present a technique for fast approximately timed simulation of software within a virtual prototyping framework. Our method performs a static analysis of the program control flow graph to construct annotations of the simulated program, combined with dynamic performance information. The static analysis estimates execution time based on a target architecture model. The delays introduced by instruction fetch and data cache misses are evaluated dynamically. At the end of each block, static and dynamic information are combined with branch target prediction to compute the total execution time of the blocks. As a result, we can provide approximate performance estimates with a high simulation speed that is still usable for software developers.

Mots clés: performance estimation; virtual prototyping; dynamic binary translation; software; processor model; approximately timed simulation; System-on-chip; computer architecture; virtual platform; Instruction Set Simulation

Domaines: Modélisation et simulation; Architectures Matérielles [cs.AR]

Vania Joloboff, Shenpeng Wang, Yangdong Deng. Fast approximately timed simulation. WIT Transactions on Information and Communication Technologies, 2015, WIT Transactions on Information and Communication Technologies, 978-1-78466-054-3 (68), pp.756. ⟨hal-01081104⟩