Fault-aware configurable logic block for reliable reconfigurable FPGAs

Chagun Basha Basheer Ahmed (1) , Sébastien Pillement (2) , Stanislaw J. Piestrak (3)

1 IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires
2 IETR - Institut d'Électronique et des Technologies du numéRique
3 IJL - Institut Jean Lamour

Reliability and other uncertainty issues are serious problems for Field Programmable Gate Arrays (FPGAs) used in mission-critical applications such as aerospace, nuclear and defense. Fortunately, today’s FPGAs have the ability to dynamically reconfigure themselves in the field, help in mitigating the effects of certain faults affecting the FPGA architecture. However, the reconfiguration process clears only the upsets created in the configuration bitstream. There are other sources of faults that might directly affect the hardware resources present in the reconfigurable FPGAs which cannot be corrected by performing configuration writeback. The nature of such faults and their consequences differ from those which occur in the configuration bitstream. This paper presents a fault-aware configurable logic block architecture to detect such faults in logic circuits and classifies it according to the nature of the fault. Fault coverage and area efficiency of the proposed architecture are discussed.

Domaines: Sciences de l'ingénieur [physics]

Chagun Basha Basheer Ahmed, Sébastien Pillement, Stanislaw J. Piestrak. Fault-aware configurable logic block for reliable reconfigurable FPGAs. IEEE International Symposium on Circuits & Systems, May 2015, Lisbonne, Portugal. pp.2732-2735, ⟨10.1109/iscas.2015.7169251⟩. ⟨hal-01104069⟩