Off-line DVFS integration in MDE-based design space exploration framework for MP2SoC systems
Abstract
As the speed metric of Massively Parallel Multi-Processors System-on-Chip (MP2SoC) systems has increased over time, another metric has become more important: power consumption. Finding a tradeoff between power consumption and performance early in the design flow of MP2SoC systems in order to satisfy time-to-market is the design challenge of Electronic Design Automation (EDA) tools. This paper presents a Design Space Exploration (DSE) framework, named Energy-Aware Rapid Design of MP2SoC (EWARDS), aiming at exploring the performance and power capabilities of modern homogenous MP2SoC systems at design time using Model-Driven Engineering (MDE) techniques. The proposed framework extends the Modeling and Analysis of Real-Time and Embedded systems (MARTE)profile with power aspects of MP2SoC systems providing a high-level design entry. In addition, EWARDS integrates an energy-aware scheduler that strives to balance performance and energy savings by combining clustering scheduling algorithm with off-line Dynamic Voltage and Frequency Scaling (DVFS) power management techniques. © 2016 IEEE.
Keywords
Clustering algorithms
Computer aided design
Design
Distributed computer systems
Dynamic frequency scaling
Electric power utilization
Embedded systems
Energy conservation
Power management
Real time systems
Scheduling
Scheduling algorithms
System-on-chip
Systems analysis
Voltage scaling
DVFS
Dynamic voltage and frequency scaling
Electronic design automation tools
EWARDS
MARTE
MP2SoC
Power management techniques
Real-time and embedded systems
Integrated circuit design