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Dynamic and Partial Reconfiguration Power Consumption Runtime Measurements Analysis for ZYNQ SoC Devices

Abstract : Field Programmable Gate Array (FPGA) architectures, such as Xilinx's Virtex-4 up to 7 series, have enabled partial and dynamic run-time self-reconfiguration for a long time. This feature enables the substitution of parts of a hardware design implemented on this re-configurable hardware, and therefore makes it possible for a system to adapt to the actual demands of applications. Dynamic Partial Reconfiguration (DPR) is an interesting technique that permits to share a part of the FPGA between different dedicated functions or hardware accelerators. Many domains may benefit from this technique including the Internet of Things (IoT), automotive industry, etc. However, many parameters, such as reconfiguration overhead, idle power consumption and performance trade-off', must be considered. In this paper, we provide a precise estimation of the power consumption when the DPR process is running in order to evaluate its influence on the performance of the global design. For this purpose, a Software/Hardware (SW/HW) system was implemented and the results were extracted in real-time using Zynq System on Chip SoC devices.
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https://hal-univ-rennes1.archives-ouvertes.fr/hal-01413269
Contributor : Laurent Jonchère <>
Submitted on : Friday, December 9, 2016 - 3:43:02 PM
Last modification on : Wednesday, October 14, 2020 - 3:52:59 AM

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  • HAL Id : hal-01413269, version 1

Citation

Mohamad Alfadl Rihani, Fabienne Nouvel, Jean-Christophe Prévotet, Mohamad Mroue, Jordane Lorandel, et al.. Dynamic and Partial Reconfiguration Power Consumption Runtime Measurements Analysis for ZYNQ SoC Devices. 13th International Symposium on Wireless Communication Systems (ISWCS), Sep 2016, Poznan, Poland. pp.592--596. ⟨hal-01413269⟩

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