Efficient parallel architecture of an intra-only scalable multi-layer HEVC encoder

R. Parois , W. Hamidouche (1) , E.G. Mora , M. Raulet , O. Deforges (1)

1 IETR - Institut d'Électronique et des Technologies du numéRique

The High Efficiency Video Coding (HEVC) standard enables meeting new video quality demands such as Ultra High Definition (UHD). Its scalable extension (SHVC) allows encoding simultaneously different representations of a video, organised in layers. Thanks to inter-layer predictions, SHVC provides bit-rate savings compared to the equivalent HEVC simulcast encoding. Therefore, SHVC seems a promising solution for both broadcast and storage applications. This paper proposes a multi-layer architecture of a pipelined software HEVC encoders with two main settings: a live setting for real-time encoding and a file setting for encoding with better fidelity. The proposed architecture provides a good trade-off between coding rate and coding efficiency achieving real-time performance of 1080p60 and 1600p30 sequences in 2× spatial scalability. Moreover, experimental results show more than a 26× and 300× speed-up for the file and live settings, respectively, with respect to the scalable reference software (SHM) in an intra-only configuration. © 2016 ECSI.

Domains: Computer Science [cs]; Networking and Internet Architecture [cs.NI]; Engineering Sciences [physics]; Electronics

R. Parois, W. Hamidouche, E.G. Mora, M. Raulet, O. Deforges. Efficient parallel architecture of an intra-only scalable multi-layer HEVC encoder. 2016 Conference on Design and Architectures for Signal and Image Processing, DASIP 2016, Oct 2016, Rennes, France. pp.11--17, ⟨10.1109/DASIP.2016.7853790⟩. ⟨hal-01508044⟩