Hypervisor Mechanisms to Manage FPGA Reconfigurable Accelerators

Tian Xia (1) , Jean-Christophe Prévotet (1) , Fabienne Nouvel (1)

1 IETR - Institut d'Électronique et des Technologies du numéRique

In the last decade, the research on CPU-FPGA hybrid architectures has become a hot topic. One of the main challenges in this domain consists in efficiently and safely managing dynamic partial reconfiguration (DPR) resources. This paper focuses on the management of the reconfiguration by an hypervisor on an ARM-FPGA platform. Using the virtualization approach, virtual machines (VM) may access resources indepen­ dently, being unaware of the existence of other VMs. The purpose of our work is to provide an abstract and transparent interface for virtual machines to access reconfigurable resources. The underlying infrastructure of partial reconfiguration management is hidden from the virtual machines, so that software developers do not need to consider the implementation details. We propose a framework where DPR accelerators are presented as virtual devices, which are universally mapped in each VM space as ordinary peripherals. The hypervisor automatically detects VM's requests for DPR resources and handles them dynamically according to a preemptive allocation mechanism. Our custom hypervisor guarantees the independent and isolation of VM domains. We also evaluate the efficiency of our framework by measuring the critical overheads during DPR management and allocations. The results demonstrate that our mechanism is implemented with low overhead.

Mots clés: micro-kernel; real-time system; FPGA; virtualization

Domaines: Systèmes embarqués

Tian Xia, Jean-Christophe Prévotet, Fabienne Nouvel. Hypervisor Mechanisms to Manage FPGA Reconfigurable Accelerators. 15th International Conference on Field-Programmable Technology, FPT 2016, Dec 2016, Xi'an, China. ⟨10.1109/FPT.2016.7929187⟩. ⟨hal-01905744⟩