Tightening Contention Delays While Scheduling Parallel Applications on Multi-core Architectures

Benjamin Rouxel 1 Steven Derrien 2 Isabelle Puaut 1
1 PACAP - Pushing Architecture and Compilation for Application Performance
Inria Rennes – Bretagne Atlantique , IRISA_D3 - ARCHITECTURE
2 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA_D3 - ARCHITECTURE
Abstract : Multi-core systems are increasingly interesting candidates for executing parallel real-time applications, in avionic, space or automotive industries, as they provide both computing capabilities and power efficiency. However, ensuring that timing constraints are met on such platforms is challenging, because some hardware resources are shared between cores. Assuming worst-case contentions when analyzing the schedulability of applications may result in systems mistakenly declared unschedulable, although the worst-case level of contentions can never occur in practice. In this paper, we present two contention-aware scheduling strategies that produce a time-triggered schedule of the application's tasks. Based on knowledge of the application's structure, our scheduling strategies precisely estimate the effective contentions, in order to minimize the overall makespan of the schedule. An Integer Linear Programming (ILP) solution of the scheduling problem is presented, as well as a heuristic solution that generates schedules very close to ones of the ILP (5 % longer on average), with a much lower time complexity. Our heuristic improves by 19% the overall makespan of the resulting schedules compared to a worst-case contention baseline.
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ACM Transactions on Embedded Computing Systems (TECS), ACM, 2017, 16 (5s), pp.1 - 20. 〈10.1145/3126496〉
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Contributeur : Isabelle Puaut <>
Soumis le : mardi 5 décembre 2017 - 21:08:54
Dernière modification le : mercredi 6 décembre 2017 - 10:22:13

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Benjamin Rouxel, Steven Derrien, Isabelle Puaut. Tightening Contention Delays While Scheduling Parallel Applications on Multi-core Architectures. ACM Transactions on Embedded Computing Systems (TECS), ACM, 2017, 16 (5s), pp.1 - 20. 〈10.1145/3126496〉. 〈hal-01655383〉

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