Efficient System-Level Hardware Synthesis of Dataflow Programs Using Shared Memory Based FIFO HEVC Decoder Case Study

Abstract : The purpose of this paper is to raise the level of abstraction in the design of embedded systems to the system-level. A novel design flow was proposed that enables an efficient hardware implementation of video processing applications described using a Domain-Specific Language (DSL) for dataflow programming. Despite the huge advancements in High-Level Synthesis (HLS) for Field-Programmable Gate Arrays (FPGAs), designers are still required to have detailed knowledge about coding techniques and the targeted architecture to achieve efficient solutions. Moreover, the main downside of the High-Level Synthesis (HLS) tools is the lack of the entire system consideration. As a remedy, in this work, we propose a design flow that combines a dataflow compiler for generating C-based High-Level Synthesis (HLS) descriptions from a dataflow description and a C-to-gate synthesizer for generating Register Transfer Level (RTL) descriptions. The challenge of implementing the communication channels of dataflow programs relying on Model of Computations (MoC) in Field-Programmable Gate Array (FPGA) is the minimization of the communication overhead. In this issue, we introduced a new interface synthesis approach that maps the large amounts of data that multimedia and image processing applications process, to shared memories on the Field-Programmable Gate Array (FPGA). This leads to a tremendous decrease in the latency and an increase in the throughput. These results were demonstrated upon the hardware synthesis of the emerging High-Efficiency Video Coding (HEVC) standard. Simulation results showed that the proposed implementation has increased throughput by a 5.2x speedup and reduced latency by a 3.8x speedup compared to a state-of-the-art implementation.