Impact of DM-LRU on WCET: A Static Analysis Approach
Résumé
Cache memories in modern embedded processors are known to improve average memory access performance. Unfortunately, they are also known to represent a major source of unpredictability for hard real-time workload. One of the main limitations of typical caches is that content selection and
replacement is entirely performed in hardware. As such, it is hard to control the cache behavior in software to favor caching of blocks that are known to have an impact on an application’s worst-case execution time (WCET).
In this paper, we consider a cache replacement policy, namely DM-LRU, that allows system designers to prioritize caching of memory blocks that are known to have an important impact on an application’s WCET. Considering a single-core, single-level cache hierarchy, we describe an abstract interpretation-based timing analysis for DM-LRU. We implement the proposed analysis in a self-contained toolkit and study its qualitative properties on a set of representative benchmarks. Apart from being useful to compute the WCET when DM-LRU or similar policies are used, the proposed analysis can allow designers to perform WCET impact-aware selection of content to be retained in cache.
Mots clés
dynamic cache locking
2012 ACM Subject Classification Computer systems organization → Real-time systems
static cache analysis
deterministic memory
WCET analysis
static cache locking
abstract interpretation
Theory of computation → Caching and paging algorithms Keywords and phrases real-time
cache profiling
LRU
Origine : Fichiers produits par l'(les) auteur(s)
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