J. Heulot, J. Boutellier, M. Pelcat, J. F. Nezan, and S. Aridhi, Applying the adaptive Hybrid Flow-Shop scheduling method to schedule a 3GPP LTE physical layer algorithm onto many-core digital signal processors, 2013 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2013), 2013.
DOI : 10.1109/AHS.2013.6604235

URL : https://hal.archives-ouvertes.fr/hal-00877643

K. Desnos, M. Pelcat, J. F. Nezan, and S. Aridhi, Pre-and post-scheduling memory allocation strategies on MPSoCs, Proceedings of the ESLsyn conference, 2013.
URL : https://hal.archives-ouvertes.fr/hal-00868945

J. Heulot, K. Desnos, J. François-nezan, M. Pelcat, M. Raulet et al., An Experimental Toolchain Based on High-Level Dataflow Models of Computation For Heterogeneous MPSoC, Proceedings of the DASIP Conference, 2012.
URL : https://hal.archives-ouvertes.fr/hal-00749175

K. Desnos, M. Pelcat, J. F. Nezan, and S. Aridhi, Memory bounds for the distributed execution of a hierarchical Synchronous Data-Flow graph, 2012 International Conference on Embedded Computer Systems (SAMOS), 2012.
DOI : 10.1109/SAMOS.2012.6404170

URL : https://hal.archives-ouvertes.fr/hal-00721335

M. Pelcat, S. Aridhi, J. Piat, and J. Nezan, Physical Layer Multi-Core Prototyping: A Dataflow-Based Approach for LTE eNodeB, 2012.
DOI : 10.1007/978-1-4471-4210-2

URL : https://hal.archives-ouvertes.fr/hal-00739957

Y. Oliva, M. Pelcat, J. Nezan, J. Prevotet, and S. Aridhi, Building a RTOS for MPSoC dataflow programming, 2011 International Symposium on System on Chip (SoC), 2011.
DOI : 10.1109/ISSOC.2011.6089218

URL : https://hal.archives-ouvertes.fr/hal-00658848

M. Pelcat, C. Bourrasset, L. Maggiani, and F. Berry, Design productivity of a high level synthesis compiler versus HDL, 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), 2016.
DOI : 10.1109/SAMOS.2016.7818341

URL : https://hal.archives-ouvertes.fr/hal-01358210

M. Pelcat, K. Desnos, L. Maggiani, Y. Liu, J. Heulot et al., Models of Architecture: Reproducible Efficiency Evaluation for Signal Processing Systems, 2016 IEEE International Workshop on Signal Processing Systems (SiPS), 2016.
DOI : 10.1109/SiPS.2016.29

URL : https://hal.archives-ouvertes.fr/hal-01390508

M. Pelcat, K. Desnos, J. Heulot, C. Guy, J. Nezan et al., Preesm: A dataflow-based rapid prototyping framework for simplifying multicore DSP programming, 2014 6th European Embedded Design in Education and Research Conference (EDERC), 2014.
DOI : 10.1109/EDERC.2014.6924354

URL : https://hal.archives-ouvertes.fr/hal-01059313

J. Heulot, M. Pelcat, K. Desnos, J. François-nezan, and S. Aridhi, Spider: A Synchronous Parameterized and Interfaced Dataflow-based RTOS for multicore DSPS, 2014 6th European Embedded Design in Education and Research Conference (EDERC), 2014.
DOI : 10.1109/EDERC.2014.6924381

URL : https://hal.archives-ouvertes.fr/hal-01067052

K. Desnos, M. Pelcat, J. Nezan, S. S. Bhattacharyya, and S. Aridhi, PiMM: Parameterized and Interfaced dataflow Meta-Model for MPSoCs runtime reconfiguration, 2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2013.
DOI : 10.1109/SAMOS.2013.6621104

URL : https://hal.archives-ouvertes.fr/hal-00877492

J. Piat, S. S. Bhattacharyya, and M. Raulet, Interface-based hierarchy for synchronous data-flow graphs, 2009 IEEE Workshop on Signal Processing Systems, 2009.
DOI : 10.1109/SIPS.2009.5336240

URL : https://hal.archives-ouvertes.fr/hal-00440478

B. D. Theelen, T. Mcw-geilen, . Basten, S. V. Voeten, S. Gheorghita et al., A scenario-aware dataflow model for combined long-run average and worst-case performance analysis, MEMOCODE, 2006.
DOI : 10.1109/memcod.2006.1695924

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.80.2351

M. Pelcat, S. Aridhi, J. Piat, and J. Nezan, Physical Layer Multi-Core Prototyping: A Dataflow-Based Approach for LTE eNodeB, 2012.
DOI : 10.1007/978-1-4471-4210-2

URL : https://hal.archives-ouvertes.fr/hal-00739957

H. Nikolov, T. Stefanov, and E. Deprettere, Modeling and FPGA Implementation of Applications Using Parameterized Process Networks with Non-Static Parameters, 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05), 2005.
DOI : 10.1109/FCCM.2005.47

B. Bhattacharya and S. S. Bhattacharyya, Parameterized dataflow modeling for dsp systems, Signal Processing IEEE Transactions on, 2001.
DOI : 10.1109/78.950795

URL : http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.22.9370&rep=rep1&type=pdf

E. A. Lee and D. G. Messerschmitt, Synchronous data flow, Proceedings of the IEEE, 1987.
DOI : 10.1109/PROC.1987.13876

A. Bouakaz, J. Talpin, and J. Vitek, Affine Data-Flow Graphs for the Synthesis of Hard Real-Time Applications, 2012 12th International Conference on Application of Concurrency to System Design, 2012.
DOI : 10.1109/ACSD.2012.16

URL : https://hal.archives-ouvertes.fr/hal-00763387

P. H. Joost, S. J. Hausmans, M. H. Geuns, M. J. Wiggers, and . Bekooij, Compositional temporal analysis model for incremental hard real-time system design, EMSOFT '12 Proceedings, 2012.

J. S. Ostroff, Abstraction and composition of discrete real-time systems, Proc. of CASE, 1995.

S. Neuendorffer and E. Lee, Hierarchical reconfiguration of dataflow models, Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2004. MEMOCODE '04., 2004.
DOI : 10.1109/MEMCOD.2004.1459852

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.10.5012

J. Heulot, M. Pelcat, J. Nezan, Y. Oliva, S. Aridhi et al., Just-in-time scheduling techniques for multicore signal processing systems, 2014 IEEE Global Conference on Signal and Information Processing (GlobalSIP), 2014.
DOI : 10.1109/GlobalSIP.2014.7032071

URL : https://hal.archives-ouvertes.fr/hal-01101790

. Kalray, MPPA MANYCORE: a multicore processors family

. Adapteva, Epiphany: A breakthrough in parallel processing

P. Helle, H. Lakshman, M. Siekmann-stegemann, T. Hinz, H. Schwarz et al., A Scalable Video Coding Extension of HEVC, 2013 Data Compression Conference, 2013.
DOI : 10.1109/DCC.2013.28

P. Marwedel, J. Teich, G. Kouveli, I. Bacivarov, L. Thiele et al., Mapping of applications to MPSoCs, Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, CODES+ISSS '11, 2011.
DOI : 10.1145/2039370.2039390

E. Lee and S. Ha, Scheduling strategies for multiprocessor real-time DSP, IEEE Global Telecommunications Conference, 1989, and Exhibition. 'Communications Technology for the 1990s and Beyond, 1989.
DOI : 10.1109/GLOCOM.1989.64160

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.73.7946

A. Kumar-singh, M. Shafique, A. Kumar, and J. Henkel, Mapping on multi/many-core systems: Survey of current and emerging trends, Proceedings of the DAC conference, 2013.

L. Dagum and R. Menon, OpenMP: an industry standard API for shared-memory programming, IEEE Computational Science and Engineering, vol.5, issue.1, 1998.
DOI : 10.1109/99.660313

E. John, D. Stone, G. Gohara, and . Shi, Opencl: A parallel programming standard for heterogeneous computing systems, Computing in science & engineering, 2010.

F. George, W. Zaki, . Plishker, S. Shuvra, C. Bhattacharyya et al., Integration of dataflow-based heterogeneous multiprocessor scheduling techniques in gnu radio, Journal of Signal Processing Systems, 2013.

S. Sriram and S. S. Bhattacharyya, Embedded multiprocessors: Scheduling and synchronization, 2012.
DOI : 10.1201/9781420048025

Y. Kwok, High-performance algorithms for compile-time scheduling of parallel processors, 1997.

E. Lee and D. G. Messerschmitt, Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing, IEEE Transactions on Computers, vol.36, issue.1, 1987.
DOI : 10.1109/TC.1987.5009446

J. Boutellier, S. Shuvra, O. Bhattacharyya, and . Silvén, A lowoverhead scheduling methodology for fine-grained acceleration of signal processing systems, Journal of Signal Processing Systems, 2010.

J. Heulot, Runtime multicore scheduling techniques for dispatching parameterized signal and vision dataflow applications on heterogeneous MPSoCs, 2015.
URL : https://hal.archives-ouvertes.fr/tel-01301642

Z. Zhou, W. Plishker, S. Shuvra, K. Bhattacharyya, M. Desnos et al., Scheduling of Parallelized Synchronous Dataflow Actors for Multicore Signal Processing, Journal of Signal Processing Systems, vol.12, issue.7, 2016.
DOI : 10.1109/SiPS.2011.6088945

URL : https://hal.archives-ouvertes.fr/hal-01075092

M. Ammar, M. Baklouti, M. Pelcat, K. Desnos, and M. Abid, Marte to ?sdf transformation for data-intensive applications analysis, Proceedings of the DASIP Conference, 2014.
DOI : 10.1109/dasip.2014.7115622

K. Desnos, Memory Study and Dataflow Representations for Rapid Prototyping of Signal Processing Applications on MPSoCs, 2014.
URL : https://hal.archives-ouvertes.fr/tel-01127297

K. Desnos, M. Pelcat, J. F. Nezan, and S. Aridhi, Memory bounds for the distributed execution of a hierarchical Synchronous Data-Flow graph, 2012 International Conference on Embedded Computer Systems (SAMOS), 2012.
DOI : 10.1109/SAMOS.2012.6404170

URL : https://hal.archives-ouvertes.fr/hal-00721335

J. Piat, Data flow modelling and optimization of loops for multicore architectures, 2010.
URL : https://hal.archives-ouvertes.fr/tel-00564522

K. Desnos, M. Pelcat, J. F. Nezan, and S. Aridhi, Pre-and post-scheduling memory allocation strategies on MP- SoCs, Proceedings of the ESLsyn conference, 2013.

K. Desnos, M. Pelcat, J. Nezan, and S. Aridhi, Memory Analysis and Optimized Allocation of Dataflow Applications on Shared-Memory MPSoCs, Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (JSPS), 2014.
DOI : 10.1145/216585.216588

URL : https://hal.archives-ouvertes.fr/hal-01083576

K. Desnos, M. Pelcat, J. Nezan, and S. Aridhi, Buffer merging technique for minimizing memory footprints of Synchronous Dataflow specifications, 2015 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2015.
DOI : 10.1109/ICASSP.2015.7178142

URL : https://hal.archives-ouvertes.fr/hal-01146340

K. Desnos, M. Pelcat, J. F. Nezan, and S. Aridhi, On Memory Reuse Between Inputs and Outputs of Dataflow Actors, ACM Transactions on Embedded Computing Systems, vol.15, issue.2, p.2016
DOI : 10.1109/TEST.2002.1041777

URL : https://hal.archives-ouvertes.fr/hal-01284333

K. Desnos, M. Pelcat, J. Nezan, and S. Aridhi, Distributed Memory Allocation Technique for Synchronous Dataflow Graphs, 2016 IEEE International Workshop on Signal Processing Systems (SiPS), 2016.
DOI : 10.1109/SiPS.2016.16

URL : https://hal.archives-ouvertes.fr/hal-01390486

T. Mudge, Computer power: A first-class architectural design constraint, IEEE Computer Magazine, 2001.
DOI : 10.1109/2.917539

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.24.6014

S. Holmbacka, E. Nogues, M. Pelcat, S. Lafond, J. Lilius et al., Energy efficiency and performance management of B I, p.133

S. Holmbacka, E. Nogues, M. Pelcat, S. Lafond, D. Menard et al., Energy-Awareness and Performance Management with Parallel Dataflow Applications, Journal of Signal Processing Systems, vol.2009, issue.2, 2015.
DOI : 10.1109/ICPP.2013.25

URL : https://hal.archives-ouvertes.fr/hal-01228447

E. Nogues, Energy optimization of Signal Processing on MPSoCs and its Application to Video Decoding, 2016.
URL : https://hal.archives-ouvertes.fr/tel-01359031

G. David and . Luenberger, Optimization by vector space methods, 1969.

E. Nogues, J. Heulot, G. Herrou, L. Robin, M. Pelcat et al., Erwan Raffin, and Wassim Hamidouche. Efficient DVFS for low power HEVC software decoder, Journal of Real- Time Image Processing, 2016.

A. Mercat, W. Hamidouche, M. Pelcat, and D. Menard, Estimating encoding complexity of a real-time embedded software HEVC codec, 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016.
DOI : 10.1109/DASIP.2016.7853792

URL : https://hal.archives-ouvertes.fr/hal-01498474

A. Mercat, F. Arrestier, W. Hamidouche, M. Pelcat, and D. Menard, Energy reduction opportunities in an HEVC real-time encoder, 2017 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2017.
DOI : 10.1109/ICASSP.2017.7952338

URL : https://hal.archives-ouvertes.fr/hal-01498493

A. Mercat, F. Arrestier, W. Hamidouche, M. Pelcat, and D. Menard, Constrain the Docile CTUs: An In-Frame complexity allocator for HEVC Intra encoders, 2017 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2017.
DOI : 10.1109/ICASSP.2017.7952339

URL : https://hal.archives-ouvertes.fr/hal-01498495

K. Desnos, S. El-assad, A. Arlicot, M. Pelcat, and D. Menard, Efficient multicore implementation of an advanced generator of discrete chaotic sequences, The 9th International Conference for Internet Technology and Secured Transactions (ICITST-2014), pp.31-36, 2014.
DOI : 10.1109/ICITST.2014.7038770

URL : https://hal.archives-ouvertes.fr/hal-01094677

R. Lazcano, D. Madroñal, K. Desnos, M. Pelcat, R. Guerra et al., Parallelism Exploitation of a Dimensionality Reduction Algorithm Applied to Hyperspectral Images, Proceedings of the DASIP Conference, 2016.
URL : https://hal.archives-ouvertes.fr/hal-01415948

E. Erwan-raffin, W. Nogues, S. Hamidouche, M. Tomperi, D. Pelcat et al., Low power hevc software decoder for mobile devices, Journal of Real-Time Image Processing, 2016.

C. Sau, F. Palumbo, M. Pelcat, J. Heulot, E. Nogues et al., Challenging the best HEVC fractional pixel FPGA interpolators with reconfigurable and multi-frequency approximate computing, IEEE Embedded Systems Letters, 2017.
DOI : 10.1109/les.2017.2703585

J. Zhang, J. Nezan, M. Pelcat, and J. Cousin, Real-time gpu-based local stereo matching method, Proceedings of the DASIP Conference, 2013.

K. Abdelouahab, C. Bourrasset, M. Pelcat, F. Berry, J. Quinton et al., A Holistic Approach for Optimizing DSP Block Utilization of a CNN implementation on FPGA, Proceedings of the 10th International Conference on Distributed Smart Camera, ICDSC '16, 2016.
DOI : 10.1109/SBAC-PADW.2014.18

URL : https://hal.archives-ouvertes.fr/hal-01415955

G. Martin and G. Smith, High-Level Synthesis: Past, Present, and Future, IEEE Design & Test of Computers, vol.26, issue.4, 2009.
DOI : 10.1109/MDT.2009.83

H. Ren, A brief introduction on contemporary High-Level Synthesis, 2014 IEEE International Conference on IC Design & Technology, 2014.
DOI : 10.1109/ICICDT.2014.6838614

J. Eker and J. Janneck, Cal language report: Specification of the cal actor language, 2003.

J. Sérot and F. Berry, High-Level Dataflow Programming for Reconfigurable Computing, 2014 International Symposium on Computer Architecture and High Performance Computing Workshop, 2014.
DOI : 10.1109/SBAC-PADW.2014.18

. Synflow, The Cx programming language, pp.2015-2024

O. Grodzevich and O. Romanko, Normalization and other topics in multi-objective optimization, Proceedings of the Fields - MITACS Industrial Problems Workshop, 2006.

M. Birem and F. Berry, DreamCam: A modular FPGA-based smart camera architecture, Journal of Systems Architecture, vol.60, issue.6, 2014.
DOI : 10.1016/j.sysarc.2014.01.006

V. Pedroni, Circuit design with VHDL, 2004.

B. Kienhuis, E. Deprettere, K. Vissers, P. Van, and . Wolf, An approach for quantitative analysis of application-specific dataflow architectures, Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors, 1997.
DOI : 10.1109/ASAP.1997.606839

A. Stevens, Introduction to amba 4 ace and big.little processing technology, 2011.

J. Eker, J. Janneck, E. Lee, J. Liu, X. Liu et al., Taming heterogeneity - the Ptolemy approach, Proceedings of the IEEE, 2003.
DOI : 10.1109/JPROC.2002.805829

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.12.8244

F. Bellard, QEMU, a Fast and Portable Dynamic Translator, USENIX Annual Technical Conference, FREENIX Track, 2005.

N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi et al., Somayeh Sardashti, and others. The gem5 simulator, ACM SIGARCH Computer Architecture News, 2011.

B. Kienhuis, E. F. Deprettere, P. Van-der, K. Wolf, and . Vissers, A Methodology to Design Programmable Embedded Systems, Embedded processor design challenges, 2002.
DOI : 10.1007/3-540-45874-3_2

M. Pelcat, Models of Architecture for DSP Systems Handbook of signal processing systems, 2017.

H. Peter, . Feiler, P. David, and . Gluch, Model-based engineering with AADL: an introduction to the SAE architecture analysis & design language, 2012.

S. International, Architecture analysis and design language (aadl) http://standards .sae.org/as5506c, p.2012

G. Lasnier, B. Zalila, L. Pautet, and J. Hugues, Ocarina : An Environment for AADL Models Analysis and Automatic Code Generation for High Integrity Applications, International Conference on Reliable Software Technologies, 2009.
DOI : 10.1109/ISORC.2008.27

P. H. Feiler, D. P. Gluch, and J. J. Hudak, The architecture analysis & design language (AADL): An introduction, 2006.
DOI : 10.21236/ADA455842

M. Larsen, Modelling field robot software using aadl, Technical Report Electronics and Computer Engineering, 2016.

M. Pelcat, A. Mercat, K. Desnos, L. Maggiani, Y. Liu et al., Models of Architecture: Application to ESL Model-Based Energy Consumption Estimation . Research report, IETR/INSA Rennes ; Scuola Superiore Sant, 2017.
URL : https://hal.archives-ouvertes.fr/hal-01464856

P. Van and R. , Programming paradigms for dummies: What every programmer should know. New computational paradigms for computer music, 2009.

M. Gondo, F. Arakawa, and M. Edahiro, Establishing a standard interface between multi-manycore and software tools - SHIM, 2014 IEEE COOL Chips XVII, 2014.
DOI : 10.1109/CoolChips.2014.6842946

C. Lattner and V. Adve, LLVM: A compilation framework for lifelong program analysis & transformation, International Symposium on Code Generation and Optimization, 2004. CGO 2004., 2004.
DOI : 10.1109/CGO.2004.1281665

O. Uml, Profile for MARTE: Modeling and Analysis of Real-Time Embedded Systems. Object Management Group, 2011.

M. Faugere, T. Bourbeau, R. D. Simone, and S. Gerard, MARTE: Also an UML Profile for Modeling AADL Applications, 12th IEEE International Conference on Engineering Complex Computer Systems (ICECCS 2007), 2007.
DOI : 10.1109/ICECCS.2007.29

F. Mallet and R. Simone, Marte vs. aadl for discreteevent and discrete-time domains, Languages for Embedded Systems and Their Applications, 2009.
URL : https://hal.archives-ouvertes.fr/inria-00371392

T. Grandpierre and Y. Sorel, From algorithm and architecture specifications to automatic generation of distributed real-time executives: a seamless flow of graphs transformations, First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings., 2003.
DOI : 10.1109/MEMCOD.2003.1210097

V. Kianzad and S. S. Bhattacharyya, CHARMED: a multi-objective co-synthesis framework for multi-mode embedded systems, Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004., 2004.
DOI : 10.1109/ASAP.2004.1342456

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.78.7993

A. D. Pimentel, Exploring Exploration: A Tutorial Introduction to Embedded Systems Design Space Exploration, IEEE Design & Test, vol.34, issue.1, 2017.
DOI : 10.1109/MDAT.2016.2626445

M. Pelcat, J. Nezan, J. Piat, J. Croizer, and S. Aridhi, A systemlevel architecture model for rapid prototyping of heterogeneous multicore embedded systems, Proceedings of DASIP conference, 2009.
URL : https://hal.archives-ouvertes.fr/hal-00429397

M. Ammar, M. Baklouti, M. Pelcat, K. Desnos, and M. Abid, Automatic Generation of S-LAM Descriptions from UML/MARTE for the DSE of Massively Parallel Embedded Systems, Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing 2015, 2016.
DOI : 10.1007/978-3-319-23509-7_14

URL : https://hal.archives-ouvertes.fr/hal-01252511

J. , C. Mazo, and R. Leupers, Programming Heterogeneous MP- SoCs

G. Kahn, The semantics of a simple language for parallel programming, Information Processing, 1974.

B. Goglin, Managing the topology of heterogeneous cluster nodes with hardware locality (hwloc), 2014 International Conference on High Performance Computing & Simulation (HPCS), 2014.
DOI : 10.1109/HPCSim.2014.6903671

URL : https://hal.archives-ouvertes.fr/hal-00985096

R. Aster, B. Borchers, and C. Thurber, Parameter estimation and inverse problems, 2011.

C. Douglas, . Montgomery, A. Elizabeth, G. Peck, and . Vining, Introduction to linear regression analysis, 2015.

A. Mercat, J. Nezan, D. Menard, and J. Zhang, Implementation of a Stereo Matching algorithm onto a Manycore Embedded System, 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014.
DOI : 10.1109/ISCAS.2014.6865380

K. Desnos and J. Zhang, PREESM project -stereo matching, 2017.

N. K. Bambha and S. S. Bhattacharyya, A joint power/performance optimization algorithm for multiprocessor systems using a period graph construct, Proceedings of the 13th international symposium on System synthesis, 2000.
DOI : 10.21236/ada456719

E. Nogues, M. Lacour, E. Raffin, M. Pelcat, and D. Menard, Low power software hevc decoder demo for mobile devices, Proceedings of the ICME conference, 2015.
URL : https://hal.archives-ouvertes.fr/hal-01184523

G. Martin, Let's Get Physical [review of "Physical Layer Multi-core Prototyping: A Dataflow-based approach for LTE eNodeB"], IEEE Design & Test, vol.31, issue.4, 2014.
DOI : 10.1109/MDAT.2014.2340173

J. Vanne, M. Viitanen, D. Timo, A. Hamalainen, and . Hallapuro, Comparative Rate-Distortion-Complexity Analysis of HEVC and AVC Video Codecs, IEEE Transactions on Circuits and Systems for Video Technology, 2012.
DOI : 10.1109/TCSVT.2012.2223013

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.352.4365

K. Torre and . Zedda, Cross-layer design of reconfigurable cyberphysical systems, Proceedings of the DATE Conference, 2017.

E. Nogues, D. Menard, and M. Pelcat, Algorithmiclevel approximate computing applied to energy efficient hevc decoding, IEEE Transactions on Emerging Topics in Computing, 2016.
DOI : 10.1109/tetc.2016.2593644

URL : https://hal.archives-ouvertes.fr/hal-01354638