Dual-gate and gate-ail-around polycrystalline silicon nanowires field effect transistors Simulation and characterization

Anne-Claire Salaün; B. Le Borgne; Laurent Pichon

Dual-gate and gate-ail-around polycrystalline silicon nanowires field effect transistors Simulation and characterization

Anne-Claire Salaün ¹ B. Le Borgne ¹ Laurent Pichon ¹

1 IETR - Institut d'Electronique et de Télécommunications de Rennes

Abstract : Polycrystalline silicon nanowires (poly-SiNWs) are synthesized using side wall spacer top-down method and classical photolithography techniques. This low-temperature (≤ 600°C) fabrication process is a low cost and fully compatible with planar complementary metal oxide semiconductor (CMOS) silicon technology. Independent biasing of each gate allows a possible threshold voltage control of the bottom gate transistors (BOT) and top gate transistors (TGT). Moreover, a new gate architecture passing from 2D to 3D, surrounding-gate transistors, called Gate-All-Around (GAA) where the gate circles the nanowire channel, allows a better electrostatic gate control. Numerical modeling of dual-gate structure and simulations are performed to estimate electrons and holes concentrations in the nanowire used as active layer versus applied gate voltages. Electrical performances of top and bottom-gate transistors are analyzed highlighting oxide-semiconducting nanowire interfaces difference in top and bottom gate configurations. Finally, GAA transistors characterization show that top channel conduction dominates when bias is applied on the surrounding gate. © 2018 Electrochemical Society Inc.All rights reserved.

Keywords : CMOS integrated circuits Nanowires Metals MOS devices Oxide semiconductors Polycrystalline materials Temperature Polysilicon Threshold voltage Thin film transistors Complementary metal oxide semiconductors Dual-gate structure Electrical performance Electrons and holes Fabrication process Semiconducting nanowires Silicon Technologies Surrounding gate transistors Field effect transistors

Document type :

Conference papers

Domain :

Engineering Sciences [physics]

Complete list of metadatas

https://hal-univ-rennes1.archives-ouvertes.fr/hal-02042765
Contributor : Laurent Jonchère <>
Submitted on : Wednesday, February 20, 2019 - 3:36:59 PM
Last modification on : Thursday, May 23, 2019 - 2:20:25 PM

Dual-gate and gate-ail-around polycrystalline silicon nanowires field effect transistors Simulation and characterization

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Dual-gate and gate-ail-around polycrystalline silicon nanowires field effect transistors Simulation and characterization

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